/*
 * Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
 * Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "example.h"
#include <iostream>
#define iter 10

int main() {

    int size = 512;
    int in[size * iter];
    int a[size];

    int out[size * iter];

    for (int i = 0; i < size; i++) {
        in[i] = i;
        a[i] = i;
    }

    transfer_kernel(in, out, size);

    int var;
    for (int j = 0; j < iter; j++) {
        for (int i = 0; i < size; i++) {
            if (out[i] != a[i]) {
                std::cout << "design fails"
                          << " i " << i << " out " << out[i] << " a " << a[i]
                          << std::endl;
                return 1;
            }
        }
    }
    return 0;
}
